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MCP601/602/603/604
2.7V to 5.5V Single Supply CMOS Op Amps
FEATURES
* * * * * * * * * Specifications rated from 2.7V to 5.5V supplies Rail-to-rail swing at output Common-mode input swing below ground 2.8MHz GBWP Unity gain stable Low power IDD = 325A max Chip Select capability with MCP603 Industrial temperature range (-40C to 85C) Available in single, dual and quad
PACKAGES
MCP601
PDIP, SOIC, TSSOP
NC 1 -IN 2 +IN 3 VSS 4 8 NC
MCP602
PDIP, SOIC, TSSOP
OUTA 1 -INA 2 +INA 3 VSS 4 8 VDD
+
7 VDD 6 OUT 5 NC
-+
B +-
A
7 OUTB 6 -INB 5 +INB
APPLICATIONS
* * * * * * * Portable Equipment A/D Converter Driver Photodiode Pre-amps Analog Filters Data Acquisition Notebooks and PDAs Sensor Interface
MCP603
PDIP, SOIC, TSSOP
NC 1 -IN 2 +IN 3 VSS 4 8 CS OUTA 1 -INA 2 +INA 3 VDD 4 +INB 5 -INB 6 OUTB 7
MCP604
PDIP, SOIC, TSSOP
14 OUTD
+
7 VDD 6 OUT 5 NC
-A+
+
D-
13 -IND 12 +IND 11 VSS 10 +INC
-B+
+
C
-
9 -INC 8 OUTC
AVAILABLE TOOLS
* Spice Macromodels (at www.microchip.com) * FilterLabTM Software (at www.microchip.com)
(c) 1999 Microchip Technology Inc.
TYPICAL APPLICATION
DESCRIPTION
The Microchip Technology Inc. MCP601/602/603/604 family of low power operational amplifiers are offered in single (MCP601), single with a Chip Select pin feature (MCP603), dual (MCP602) and quad (MCP604) configurations. These operational amplifiers (op amps) utilize an advanced CMOS technology, which provides low bias current, high speed operation, high open-loop gain and rail-to-rail output swing. This product offering operates with a single supply voltage that can be as low as 2.7V, while drawing less than 325A of quiescent current. In addition, the common-mode input voltage range goes 0.3V below ground, making these amplifiers ideal for single supply operation. These devices are appropriate for low-power battery operated circuits due to the low quiescent current, for A/D Converter driver amplifiers because of their wide bandwidth, or for anti-aliasing filters by virtue of their low input bias current.
VIN -IN VDD VOUT OUT
MCP60X
+IN VREF Low Input Bias Current Over Temperature VSS
Rail-to-Rail Output Swing
2nd Order Low Pass Filter The MCP601, MCP602 and MCP603 are available in standard 8-lead PDIP, SOIC and TSSOP packages. The quad MCP604 is offered in 14-lead PDIP, SOIC and TSSOP packages. PDIP and SOIC packages are fully specified from -40C to +85C with power supplies from 2.7V to 5.5V.
(c) 1999 Microchip Technology Inc.
DS21314C-page 1
MCP601/602/603/604
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME +IN, +INA, +INB, +INC, +IND -IN, -INA, -INB, -INC, -IND VDD VSS FUNCTION Non-inverting Input Terminals Inverting Input Terminals Positive Power Supply Negative Power Supply
VDD ..................................................................................7.0V All inputs and outputs w.r.t. ............. VSS -0.3V to VDD +0.3V Difference Input voltage ....................................... |VDD - VSS| Output Short Circuit Current .................................continuous Current at Input Pin .......................................................2mA Current at Output and Supply Pins .............................30mA Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-55C to +125C Soldering temperature of leads (10 seconds) ............. +300C *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
OUT, OUTA, OUTB, OUTC, OUTD Output Terminals CS NC Chip Select No internal connection to IC
DC CHARACTERISTICS
Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25 C, VCM = VDD/2, RL = 100k to VDD/2, and VOUT ~ VDD/2 PARAMETERS INPUT OFFSET VOLTAGE Input Offset Voltage Over Temperature(1) Drift with Temperature Power Supply Rejection INPUT CURRENT AND IMPEDANCE Input Bias Current Over Temperature(1) SYMBOL VOS VOS dVOS/dT PSRR IB IB IOS ZCM ZDIFF VCM CMRR VSS-0.3 75 90 MIN -2 -3 2.5 40 1 20 1 1013||6 1013||3 VDD-1.2 60 100 TYP MAX +2 +3 UNITS mV mV V/C V/V pA pA pA ||pF ||pF V dB VDD = 5V, VCM = 0 to 3.8V RL = 25k to VDD/2, 50mV < VOUT < (VDD - 50 mV) RL = 5k to VDD/2, 100mV < VOUT < (VDD - 100mV) RL = 25k to VDD/2 RL = 5k to VDD/2 RL = 25k to VDD/2, AOL 100dB RL = 5k to VDD/2, AOL 95dB VOUT = 2.5V, VDD = 5V TA= -40C to +85C TA= -40C to +85C TA= -40C to +85C for VDD = 2.7V to 5.5V CONDITIONS
Input Offset Bias Current Common Mode Input Impedance Differential Input Impedance COMMON MODE Common-Mode Input Range Common-Mode Rejection Ratio OPEN LOOP GAIN DC Open Loop Gain
AOL
100
110
dB
DC Open Loop Gain
AOL
95
102
dB
OUTPUT Low Level/High Level Output Swing
VOL, VOH VOL, VOH
VSS + 0.015 VSS + 0.045 VSS + 0.050 VSS + 0.100 20
VDD - 0.020 VDD - 0.060 VDD - 0.050 VDD - 0.100
V V V V mA
Linear Region Maximum Output Voltage Swing
VOUT VOUT
Output Short Circuit Current POWER SUPPLY Supply Voltage Quiescent Current Per Amp
ISC
VDD IQ
2.7 230
5.5 325
V A IL = 0
Note 1: Max. and Min. specified for PDIP and SOIC packages only. Typical refers to all packages.
DS21314C-page 2
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
AC CHARACTERISTICS
Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 100k to VDD/2, and VOUT ~ VDD/2 PARAMETERS Gain Bandwidth Product Phase Margin Slew Rate Setting Time to 0.01% SYMBOL GBWP m SR MIN TYP 2.8 50 2.3 4.5 MAX UNITS MHz degrees V/s s CONDITIONS VDD = 5V CL = 50pF, VDD = 5V G = +1V/V, VDD = 5V for VOUT = 3.8VSTEP, CL = 50pF, VDD = 5V, G = +1V/V
NOISE Input Voltage Noise Input Voltage Noise Density Input Current Noise Density en en in 7 29 0.6 VP-P nV/ Hz fA/ Hz f = 0.1Hz to 10Hz f = 1kHz f = 1kHz
SPECIFICATIONS FOR MCP603 CHIP SELECT FEATURE
Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 100k to VDD/2, and VOUT ~ VDD/2 PARAMETERS CS LOW SPECIFICATIONS CS Logic Threshold, Low CS Input Current, Low Amplifier Output Leakage, CS High CS HIGH SPECIFICATIONS CS Logic Threshold, High CS Input High, Shutdown CS Pin Current CS Input High, Shutdown GND Current DYNAMIC SPECIFICATIONS CS Low to Amplifier Output High Turn-on Time CS High to Amplifier Output High Z CS Threshold Hysteresis tON tOFF 3.1 100 0.3 10 s ns V CS low 0.2VDD CS high 0.8VDD, No Load VIH ICSH IQ 0.8 VDD 0.51 VDD 0.7 0.7 VDD 2.0 2.0 V A A For entire VDD range CS = VDD CS = VDD VIL ICSL VSS -1.0 1 0.42 VDD 0.2 VDD V A nA For entire VDD range CS = 0.2VDD SYMBOL MIN TYP MAX UNITS CONDITIONS
TEMPERATURE SPECIFICATIONS
Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND PARAMETERS TEMPERATURE RANGE Specified Temperature Range Operating Temperature Range Storage Temperature Range THERMAL PACKAGE RESISTANCE Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-TSSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP JA JA JA JA JA JA 85 163 124 70 120 100 C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 +85 +85 +150 C C C SYMBOL MIN TYP MAX UNITS CONDITIONS
(c) 1999 Microchip Technology Inc.
DS21314C-page 3
MCP601/602/603/604
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25C, VCM = VDD/2, RL = 25k to VDD/2 and VOUT ~ VDD/2
260 IL = 0 Quiescent Current per Amplifier (A) 240 220 200 180 160 140 120 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply, VDD (V)
120 100 Open Loop Gain (dB) 80 60 40 20 0 -20 -40 -60 0 0.1 Phase Gain
100 50 0 -50 -100 -150 -200
-250 10 1000 100000 10000000 10 1K 100K 10M Frequency (Hz)
FIGURE 2-1: Frequency
Open Loop Gain, Phase Margin vs.
Phase Margin (degrees)
CL = 50pF, RL = 100k VDD = 5V
200 150
FIGURE 2-4:
Quiescent Current vs. Power Supply
300
3 Slew Rate (V/s)
High-to-Low Transition
CL=50pF, RL=100k, VDD=5V
Quiescent Current per Amplifier (A)
3.5
280 260 240 220 200 180 160 140 120 100
VDD = 2.7V VDD = 5.5V
IL=0
2.5 Low-to-High Transition
2
1.5
1 -40 -20 0 20 40 60 80 Temperature (C)
-40
-20
0
20
40
60
80
Temperature (C)
FIGURE 2-2:
Slew Rate vs. Temperature
FIGURE 2-5:
10000 Input Voltage Noise Density (nV/ Hz)
Quiescent Current vs. Temperature
4.5 4 Gain Bandwidth Product (MHz) 3.5 3 2.5 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80 Temperature (C) Phase CL = 55pF Gain Bandwidth Product
85 80 Phase Margin (degrees) 75 70 65 60 55 50 45 40
RL = 10k
1000
100
10 0.1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 2-3: Temperature
Gain Bandwidth Product vs.
FIGURE 2-6: Frequency
Input
Voltage
Noise
Density
vs.
DS21314C-page 4
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25C, VCM = VDD/2, RL = 25k to VDD/2 and VOUT ~ VDD/2
500 400 300 Offset Voltage (V) 200 100 0 -100 -200 -300 -400 -500 -40 -20 0 20 40 60 80 Temperature (C) VDD = 5.5V VDD = 2.7V RL = 100k Common Mode Rejection Ratio, Power Supply Rejection Ratio (dB)
95 100
CMRR VDD = 2.7V VCM = -0.3V to 1.5V PSRR, VDD = 2.7V to 5.5V CMRR VDD = 5.5V VCM = -0.3V to 4.3V
90
85
80
75 -40 -20 0 20 40 60 80
Temperature ( C)
FIGURE 2-7: Normalized Offset Voltage vs. Temperature with VDD = 2.7V
FIGURE 2-10: Common-Mode Rejection Ratio, Power Supply Rejection Ratio vs. Temperature
240 220 200 Offset Voltage (V) 180 160 140 120 100 80 60 40 -1 0 1 2 3 4 5 Common Mode Voltage (V) VDD = 2.7V VDD = 5.5V Representative Part
100 80
PSRR, CMRR (dB)
PSRR+ PSRRCMRR
VDD=5.0V, CL=50 pF
60 40 20 0 -20
1 10 1.E+00 1.E+01
100 1.E+02
1K 10K 1.E+03 1.E+04
Frequency (Hz)
100K 1.E+05
1M 1.E+06
10M 1.E+07
FIGURE 2-8: Voltage
Offset Voltage vs. Common-Mode
FIGURE 2-11: Common-Mode Rejection Power Supply Rejection Ratio vs. Frequency
Ratio,
20 Input Bias Current, Input Offset Current (pA) 18 16 14 12 10 8 6 4 2 0 -40 -20 0 20 40 60 80 Temperature (C) Input Bias Current Levels are Typically less than 1pA Below 25C Input Bias Current
Input Bias, Input Offset Current (pA)
20
VDD = 5.5V
18 16 14 12 10 8 6 4 2 0 0
VDD = 5.5V RL = TA = 85C Input Bias Current
Input Offset Current
Input Offset
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Common-mode Voltage (V)
FIGURE 2-9: Input Bias Current, Input Offset Current vs. Temperature
FIGURE 2-12: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage
(c) 1999 Microchip Technology Inc.
DS21314C-page 5
MCP601/602/603/604
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 25k to VDD/2 and VOUT ~ VDD/2
120 VDD = 5.5V DC Open Loop Gain (dB)
115
Open Loop Gain (dB)
110
110
VDD = 2.7V 100
105
100
90
95
80
0 0
2K 20000
4K 40000
6K 60000
8K 80000
10K 100000
90 2 2.5 3 3.5 4 4.5 5 5.5 Power Supply Voltage, VDD (V)
Load Resistance ()
FIGURE 2-13: DC Open Loop Gain vs. Output Load
FIGURE 2-16: DC Open Loop Gain vs. Power Supply
120
3.5 Gain-Bandwidth 3 Gain-Bandwidth (MHz) 2.5 2 90 100
115 DC Open Loop Gain (dB)
Phase Margin (degrees)
110 105 100 95 90 85
80 70 60 Phase Margin 50 40 30
VDD = 5.5V, VOUT = 50mV to 5.45V
1.5 1 VDD = 5.0V, CL= 50 pF
VDD = 2.7V, VOUT = 50mV to 2.65V
0.5 0
100 100
1K 10K 1000 10000 Load Resistance ()
100K 100000
80 -40 -20 0 20 40 Temperature (C) 60 80
FIGURE 2-14: Gain Bandwidth, Phase Margin vs. Load Resistance
FIGURE 2-17: DC Open Loop Gain vs. Temperature
700 600 VDD-VOH, VOL-VSS (mV) 500 400 300 200 100 0 VOL - VSS VDD=2.7V VDD-VOH VDD=5.5V VOL - VSS VDD=5.5V VDD-VOH VDD=2.7V
12 10 8 6 4 2 0 VOL-VSS, VDD=2.7V VDD-VOH, VDD=5.5V
VOH, VOL (mV)
VOL-VSS, VDD=5.5V VDD-VOH, VDD=2.7V
100
100
1000
1K
10000
10K
100000
100K
-40
-20
0
20 Temperature (C)
40
60
80
Load Resistance ()
FIGURE 2-15: Low Level and High Level Output Swing vs. Resistive Load
FIGURE 2-18: Low Level and High Level Output Swing vs. Temperature
DS21314C-page 6
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 25k to VDD/2 and VOUT ~ VDD/2
VDD = 5V RL = 100k CL = 50pF G = +1V/V 500 mV/div
CL=50pF, RL=100k, VDD = 5V, G= -1V/V
500 mV/div
1S / div
1S / div
FIGURE 2-19: Large Signal Non-Inverting Signal Pulse Response
FIGURE 2-22: Large Signal Inverting Signal Pulse Response
VDD = 5V RL = 100k
50 mV/div
50 mV/div
CL=50 pF G = +1V/V
CL=50pF, RL=100k, VDD = 5V, G= -1V/V
1S / div
1S / div
FIGURE 2-20: Small Response
Signal
Non-inverting
Pulse
FIGURE 2-23: Small Signal Inverting Signal Pulse Response
5.5 5 Full-Scale Output Voltage Swing (V) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 VDD = 5V
40 30 Short Circuit Current (mA) 20 10 0 -10 -20 -30 -40 Negative Short Circuit Current VDD = 5.5V -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Negative Short Circuit Current VDD = 2.7V Positive Short Circuit Current VDD = 2.7V Positive Short Circuit Current VDD = 5.5V
1K 1000
10K 10000
100K 100000
Frequency (Hz)
1M 1000000
10M 10000000
Temperature (C)
FIGURE 2-21: Maximum Full Scale Output Voltage Swing vs. Frequency
FIGURE 2-24: Output Temperature
Short
Circuit
Current
vs.
(c) 1999 Microchip Technology Inc.
DS21314C-page 7
MCP601/602/603/604
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 25k to VDD/2 and VOUT ~ VDD/2
100 0
500 mV/div
Amplifier Output Active
CL = 50pF G = +1V/V VIN+ = 2.5V VDD = 5V
GND Current (A)
CS
RL = 100k to GND
-100 -200 -300 -400 -500 -600 -700 -800 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CS Pin Voltage (V) VDD = 5.5V
Hi-Z
5 S/div
FIGURE 2-25: Chip Response Time
Select
to
Amplifier
Output
FIGURE 2-28: GND Current vs. CS Voltage
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 0.0
3 Internal CS Switch Output (V)
VDD = 5.5V
CS Pin Current (A)
2.5 2 1.5 1 0.5 0 -0.5 0
Amplifier Output Active (driven)
VDD = 5V
CS Input Low to High CS Input High to Low Amplifier Output in Hi-Z state
1.0
2.0
3.0
4.0
5.0
6.0
1
2
CS Pin Voltage (V)
3 4 CS Input Voltage (V)
5
6
FIGURE 2-26: Input CS Current vs. CS Voltage
FIGURE 2-29: CS Hysterisis
-150 Channel to Channel Isolation (dB) -145 -140 -135 -130 -125 -120 -115 -110 -105 -100 100 100 1000 RL =
1K
10000 Frequency (Hz)
10K
100000
100K
1000000
1M
FIGURE 2-27: Channel to Channel Separation
DS21314C-page 8
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
3.0 APPLICATIONS INFORMATION
The MCP601/602/603/604 family of operational amplifiers are fabricated on Microchip's state-of-the-art CMOS process. They are unity gain stable and suitable for a wide range of general purpose applications. With this family of operational amplifiers, the power supply pin should be by-passed with a 1F capacitor. The Linear Region Maximum Output Voltage Swing of the MCP601/602/603/604 family is specified within 50mV from the positive and negative rail with a 25k load and 100mV from the rails with a 5k load. The overriding condition that defines the linear region of the amplifier is the open loop gain that is specified over that region. In the voltage output region between VSS + 50mV and VDD - 50mV, the open loop gain is specified to 100dB (min) with a 25k load. The classical definition of the open loop gain of an amplifier is: AOL = VOUT / VOS where: AOL is the DC open loop gain of the amplifier, VOUT is equal to (VDD - 50mV) - (VSS + 50mV) for RL= 25k, and VOS is the change in offset voltage with the changing output voltage of the amplifier.
3.1
Rail-to-Rail Output Swing
There are two specifications that describe the output swing capability of the MCP601/602/603/604 family of operational amplifiers. The first specification, Low Level and High Level Output Voltage Swing, defines the absolute maximum swing that can be achieved under specified loaded conditions. For instance, the Low Level Output Voltage Swing of the MCP601/602/603/ 604 family is specified to be able to swing at least to 15mV from the negative rail with a 25k load to VDD/2. This output swing performance is shown in Figure 3-1, where the output of an MCP601 is configured in a gain of +2V/V and over driven with a 40kHz triangle wave. In this figure, the degradation of the output swing linearity is clearly illustrated. This degradation occurs after the point at which the open loop gain of the amplifier is specified and before the amplifier reaches its maximum and minimum output swing.
VOH, VOL (0.1mV/div)
3.2
Input Voltage and Phase Reversal
Since the MCP601/602/603/604 amplifier family is designed with CMOS devices, it does not exhibit phase inversion when the input pins exceed the negative supply voltage. Figure 3-2 shows an input voltage exceeding both supplies with no resulting phase inversion.
10 8 6 4 Input Signal (V) 2 0 G=+2V/V, VDD= 5V -2 0 10 20 30 40 50 Time (s) VOL VOH
0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7
Input and Output Voltage (V)
6 5 4 3 2 1 0 -1 0 10 20 Time(S) 30 40 50 Input Signal G = +2V/V VDD = 5V Output Signal
FIGURE 3-1: Swing
Low Level and High Level Output
The second specification that describes the output swing capability of these amplifiers is the Linear Region Maximum Output Voltage Swing. This specification defines the maximum output swing that can be achieved while the amplifier is still operating in its linear region.
FIGURE 3-2: The MCP601/602/603/604 family of op amps do not have phase reversal issues. For the graph, the amplifier is in a unity gain or buffer configuration.
(c) 1999 Microchip Technology Inc.
DS21314C-page 9
MCP601/602/603/604
The maximum operating common-mode voltage that can be applied to the inputs is VSS - 0.3V to VDD - 1.2V. In contrast, the absolute maximum input voltage is VSS - 0.3V and VDD + 0.3V. Voltages on the input that exceed this absolute maximum rating can cause excessive current to flow in or out of the input pins. Current beyond 2mA can cause possible reliability problems. Applications that exceed this rating must be externally limited with an input resistor as shown in Figure 3-3.
4 Gain-Bandwidth (MHz) 3.5 3 2.5 2 1.5 1 0.5 0 10 10
100 100 1E3 1000 10E3 10000 100E3 100000
80 Gain-Bandwidth VDD=5.0V, RL=100 k 70 60 50 Phase Margin 40 30 20 10 0 1E6 1000000 Phase Margin (degrees)
Capacitance (pF)
FIGURE 3-4: Gain Bandwidth, Phase Margin vs. Capacitive Load
bit
MCP60X RIN
VDD
RIN = (Maximum expected voltage - VDD) / 2mA or (VSS - Minimum expected voltage)/ 2mA. VIN
RISO MCP60X
VOUT CL
FIGURE 3-3: If the inputs of the amplifier exceed the Absolute Maximum Specifications, an input resistor, RIN , should be used to limit the current flow into that pin.
FIGURE 3-5: Amplifier circuits that can be used when driving heavy capacitive loads.
If the amplifier is required to drive larger capacitive loads, the circuit shown in Figure 3-5 can be used. A small series resistor (RISO) at the output of the amplifier improves the phase margin when driving large capacitive loads. This resistor decouples the capacitive load from the amplifier by introducing a zero in the transfer function. This zero adjusts the phase margin by approximately: m = tan-1 (2 GBWP x RISO x CL) where: m is the improvement in phase margin, GBWP is the gain bandwidth product of the amplifier, RISO is the capacitive decoupling resistor, and CL is the load capacitance
3.3
Capacitive Load and Stability
Driving capacitive loads can cause stability problems with many of the higher speed amplifiers. For any closed loop amplifier circuit, a good rule of thumb is to design for a phase margin that is no less than 45. This is a conservative theoretical value, however, if the phase margin is lower, layout parasitics can degrade the phase margin further causing a truly unstable circuit. A system phase shift of 45 will have an overshoot in its step response of approximately 25%. A buffer configuration with a capacitive load is the most difficult configuration for an amplifier to maintain stability. The Phase versus Capacitive Load of the MCP60X amplifier is shown in Figure 3-4. In this figure, it can be seen that the amplifier has a phase margin above 40, while driving capacitance loads up to 100pF.
DS21314C-page 10
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
3.4 The Chip Select Option of the MCP603
The MCP603 is a single amplifier with a Chip Select option. When CS is pulled high the supply current drops to 0.7A (typ) ,which is pulled through the CS pin to VSS. In this state, the amplifier is put into a high impedance state. By pulling CS low or letting the pin float, the amplifier is enabled. Figure 3-6 shows the output voltage and supply current response to a CS pulse. CS VIL tON Output Hi-Z 230A (typ) VDD Supply Current GND Current 2.0nA (typ) 0.7A (typ) 230A (typ) 2.0nA (typ) 0.7A (typ) VIH tOFF Hi-Z
CS Current
0.7A (typ)
2nA(typ)
0.7A (typ)
FIGURE 3-6:
Timing Diagram for the CS Function of the MCP603 Amplifier
3.5
Layout Considerations
In applications where low input bias current is critical, PC board surface leakage effects and signal coupling from trace to trace need to be taken into consideration. 3.5.1 SURFACE LEAKAGE -In +In V-
Surface leakage across a PC board is a consequence of differing DC voltages between two traces combined with high humidity, dust or contamination on the board. For instance, the typical resistance from PC board trace to pad is approximately 1012 under low humidity conditions. If an adjacent trace is biased to 5V and the input pin of the amplifier is biased at or near zero volts, a 5pA leakage current will appear on the amplifier's input node. This type of PCB leakage is five times the room temperature input bias current (1pA, typ) of the MCP601/602/603/604 family of amplifiers. The simplest technique that can be used to reduce the effects of PC board leakage is to design a ring around sensitive pins and traces. An example of this type of layout is shown in Figure 3-7.
Guard Ring
FIGURE 3-7: Example of Guard Ring for the MCP601, the A-amplifier of the MCP602 or the MCP603 in a PC Board Layout
(c) 1999 Microchip Technology Inc.
DS21314C-page 11
MCP601/602/603/604
Circuit examples of ring implementations are shown in Figure 3-8. In Figure 3-8A, B and C, the guard ring is biased to the common-mode voltage of the amplifier. This type of guard ring is most effective for applications where the common-mode voltage of the input stage changes, such as buffers, inverting gain amplifiers or instrumentation amplifiers. The strategy shown in Figure 3-8D, biases the common-mode voltage and guard ring to ground. This type of guard ring is typically used in precision photo sensing circuits. Figure 3-8A 3.5.2 SIGNAL COUPLING The input pins of the MCP601/602/603/604 amplifiers have a high impedance providing an opportunity for noise injection, if layout issues are not considered. These high impedance input terminals are sensitive to injected currents. This can occur if the trace from a high impedance input is next to a trace that has fast changing voltages, such as a digital or clock signal. When a high impedance trace is in close proximity to a trace with these types of voltage changes, charge is capacitively coupled into the high impedance trace. w x L x eo x er d
PCB Trace
C=
pF
MCP60X
L
d
w (typ 0.003mm)
Figure 3-8B
w= thickness of PCB trace
PCB Cross-Section
L= length of PCB trace d= distance between the two PCB traces
MCP60X
FIGURE 3-9: Capacitors can be built with PCB traces allowing for coupling of signals from one trace to another.
As shown in Figure 3-9, the value of the capacitance between two traces is primarily dependent on the distance (d) between the traces and the distance that the two traces are in parallel (L). From this model, the amount of current generated into the high impedance trace is equal to: I = C V/t
Figure 3-8C
MCP60X
Voltage Reference (could be ground)
where: I equals the current that appears on the high impedance trace, C equals the value of capacitance between the two PCB traces, V equals the change in voltage of the trace that is switching, and
Figure 3-8D
VDD MCP60X
t equals the amount of time that the voltage change took to get from one level to the next.
FIGURE 3-8: Examples of how to design PC Board traces to minimize leakage paths to the high impedance input pins of the MCP601/602/603/604 amplifiers.
DS21314C-page 12
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
3.6
3.6.1
Typical Applications
ANALOG FILTERS
of poles that are required for the application. Finally, the program will generate a SPICE macromodel, which can be used for spice simulations. 3.6.2 INSTRUMENTATION AMPLIFIER CIRCUITS
Examples of two second order low pass filters are shown in Figure 3-10 and Figure 3-11. The filter in Figure 3-10 can be configured for gain of +1V/V or greater. The filter in Figure 3-11 can be configured for inverting gains.
Sallen-Key
C2 VIN R1 R2 C1
MCP60X
The instrumentation amplifier has a differential input, which subtracts one analog signal from another and rejects common mode signals. This amplifier also provides a single ended analog output signal. The three op amp instrumentation amplifier is illustrated in Figure 3-12 and the two op amp instrumentation amplifier is shown in Figure 3-13.
VDD V2
MCP60X
VOUT
*
R3
R4 VDD
R3
VOUT VIN
R4
R2 RG R2 R3 R4 V1
MCP60X
*
MCP60X
s2+s(1/R1C2+1/R2C2+1/R2C1 - K/R2C1+1/R1R2C2C1) K = 1 + R4 /R3
=
K/(R1R2C2C1)
VOUT
FIGURE 3-10: 2nd Order Low Pass Sallen-Key Filter
VREF
R2 VIN R1 R3 C2
2R 2 R 4 R4 VOUT = (V1 -V 2 ) + -------- ----- + V REF ----- 1 - - R 3 RG R3 *Bypass Capacitor, 1F C1 VOUT
MCP60X
FIGURE 3-12: An instrumentation amplifier can be built using three operational amplifiers and seven resistors.
RG
VOUT VIN
=
-1/R1R3C2C1 s2C2C1 + sC1(1/R1 + 1/R2 + 1/R3) + 1/(R2R3C2C1)
R1 VREF
R2 VDD *
MCP60X
FIGURE 3-11: 2nd Order Multiple-Feedback Filter
Low
Pass
R1 R2
The MCP601/602/603/604 family of operational amplifiers are particularly well suited for these types of filters. The low input bias current, which is typically 1pA (up to 60pA at temperature), allows the designer to select higher value resistors, which in turn reduces the capacitive values. This allows the designer to select surface mount capacitors, which in turn can produce a compact layout. The rail-to-rail output operation of the MCP601/602/ 603/604 family of amplifiers make these circuits well suited for single supply operation. Additionally, the wide bandwidth allows low pass filter design up to 1/10 of the GBWP or 300kHz. These filters can be designed using the calculations provided in the Figures or with Microchip's interactive FilterLab software. FilterLab will calculate capacitor and resistor values, as well as, determine the number
V2 V1
MCP60X
VOUT
R 1 2R 1 VOUT = (V1 -V2 ) 1 + ----- + -------- + VREF R 2 RG *Bypass Capacitor, 1F
FIGURE 3-13: An instrumentation amplifier can also be built using two operational amplifiers and five resistors.
(c) 1999 Microchip Technology Inc.
DS21314C-page 13
MCP601/602/603/604
An advantage of the three op amp configuration is that it is capable of unity gain operation. A disadvantage, as compared to the two op amp instrumentation amplifier, is that the common mode range reduces with higher gains. The two op amp configuration uses fewer op amps, so power consumption is also low. Disadvantages of this configuration are that the common-mode range reduces with gain and it must be configured in gains of two or higher. 3.6.3 PHOTO DETECTION In contrast, a photodiode that is configured in the photoconductive mode has a reverse bias voltage, which is applied across the photo sensing element as shown in Figure 3-14. The width of the depletion region is reduced when this voltage is applied across the photo detector, which reduces the photodiode parasitic capacitance significantly. This reduced parasitic capacitance facilitates high speed operation, however, the linearity and offset errors are not optimized. The design trade off for this action is increased diode leakage current and linearity errors. A key amplifier specification for this application is high speed digital communication. The MCP601/602/603/604 family is well suited for medium speed photoconductive applications with their wide bandwidth and rail-to-rail output swing.
The amplifiers in the MCP601/602/603/604 family of devices can be used to easily convert the signal from a sensor that produces an output current, such as a photodiode, into a voltage. This is implemented with a single resistor and an optional capacitor in the feedback loop of the amplifier as shown in Figure 3-14. Photodiode in Photovoltaic Mode C2 R2 D1 ID1
MCP60X
Light
VOUT
Photodiode in Photoconductive Mode VBIAS D1 Light ID1
MCP60X
R2
VOUT
VOUT = R2 ID1
FIGURE 3-14: Photo Sensing Circuits Using the MCP60X Amplifier
A photodiode that is configured in the photovoltaic mode has no voltage potential placed across the element or is zero biased (Figure 3-14). In this mode, the light sensitivity and linearity is maximized making it best suited for precision applications. The key amplifier specifications for this application are low input bias current, low noise and rail-to-tail output swing. The MCP601/602/603/604 family is capable of meeting all three of these difficult requirements.
DS21314C-page 14
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
4.0 SPICE MACROMODEL
The Spice macromodel for the MCP601, MCP602, MCP603 and MCP604 simulates the typical amplifier performance of offset voltage, DC power supply rejection, input capacitance, DC common mode rejection ratio, open loop gain over frequency, phase margin with no capacitive load, output swing, DC power supply current, power supply current change with supply voltage, input common mode range and input voltage noise. The characteristics of the MCP601, MCP602, MCP603, and MCP604 amplifiers are similar in terms of performance and behavior. This single op amp macromodel supports all four devices with the exception of the chip select function of the MCP603, which is not modeled. The listing for this macromodel is shown on the next page. The most recent revision of the model can be down loaded from Microchip's web site at www.microchip.com.
(c) 1999 Microchip Technology Inc.
DS21314C-page 15
MCP601/602/603/604
* Macromodel for MCP601 (single), MCP602 (dual), MCP603 (single w/CS), and MCP604 (quad) * Revision History: * REV A : 6-30-99
created
BCB
.subckt mcp601 1 2 3 4 5 *Input Stage, pole at 5MHz M1 9 64 7 3 Ptype M2 8 2 7 3 Ptype CDIFF 1 2 3E-12 CCM1 1 4 6E-12 CCM2 2 4 6E-12 IDD 3 7 30e-6 RA 8 6 1.485e3 RB 9 6 1.485e3 CA 8 9 10.71e-12 *Input Stage Common-Mode Clamping VCMM 4 6 0.35 ECM 55 4 3 64 1 RCM 57 56 1e3 DCMP 56 55 DX VCMP 57 4 1.2 GCMP 23 4 57 56 -0.1E-3 *Input errors (vos, en, psr, cmr) ERR 64 1 poly(3) (67,4) (3, 4) (1,34) 0 1 40e-6 3.2e-6 *Second Stage, pole at 3.3Hz GS 23 4 8 9 5.7e-3 R1 23 4 0.397e9 C2 23 4 122.8e-12 VSOP 3 24 4.784 VSOM 25 4 -3.48 DSOP 23 24 DY DSOM 25 23 DY *HCM 3 3 VCMP IS 3 4 -0.132 *mid-supply reference, output swing limit RMID1 3 34 61.62E3 RMID2 4 34 61.62E3 ELEVEL 34 4 23 4 -1 *output stage DO3 34 43 DY DO4 44 34 DY DO5 3 45 DY DO6 3 46 DY DO7 4 45 DY DO8 4 46 DY VO3 43 5 0.1 VO4 5 44 0.1 GO4 3 5 3 23 10E-3 GO3 4 5 23 4 10E-3 GO1 45 4 5 23 10E-3 GO2 46 4 23 5 10E-3 RO3 3 5 100 RO4 4 5 100 * input voltage noise VN1 65 4 0.6 DN1 65 67 DX RN1 67 4 13E3 .model Ptype PMOS (L=2 W=275) .model DY D(IS=1e-15 BV =50) .model DX D(IS=1e-18 AF=0.6 KF=10e-17) .ENDS
DS21314C-page 16
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
MCP60X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP60X -- t /P
Package: P SN SL ST = = = = Plastic DIP (300 mil Body), 8-lead and 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead TSSOP, 8-lead and 14-lead
Temperature Range:
I = -40C to +85C
Device:
Single Operational Amplifier Single Operational Amplifier (Tape and Reel-SOIC/TSSOP) Dual Operational Amplifier Dual Operational Amplifier (Tape and Reel-SOIC/TSSOP) Single Operational Amplifier w/CS Function Single Operational Amplifier w/CS Function (Tape and Reel-SOIC/TSSOP) MCP604 = Quad Operational Amplifier MCP604T = Quad Operational Amplifier (Tape and Reel-SOIC/TSSOP)
MCP601 MCP601T MCP602 MCP602T MCP603 MCP603T
= = = = = =
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 1999 Microchip Technology Inc.
DS21314C-page 17
MCP601/602/603/604
NOTES:
DS21314C-page 18
(c) 1999 Microchip Technology Inc.
MCP601/602/603/604
NOTES:
(c) 1999 Microchip Technology Inc.
DS21314C-page 19
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DS21314C-page 20
(c) 1999 Microchip Technology Inc.

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